With the continued scaling of IC technology, due to the large amount of electronic circuits on a small area, the density of chip input/output connection pads (I/O's) continues to increase. It becomes increasingly difficult for traditional IC packaging technologies to deal with this high density and to enable fan-out routing to a large I/O pitch. This is becomes even more stringent when dealing with 3D-IC stacks.
A solution is to use a package that re-arranges or converts the input/output pitch of the die to a larger pitch area array that can be handled by the system level printed circuit board. This typically results in a package size that is several times larger than the stack itself. In order to obtain such a re-arrangement, one solution is the use of a silicon-based interconnect substrate. The die or stack of dies is assembled to this substrate which provides adequate interconnect and wiring density. If this Si-interposer also has through-Si via connections, a device with a high density of area-array connections may result. To protect the die, this interposer substrate may be encapsulated by a wafer-level transfer moulding encapsulation process. After dicing, the final Si-interposer package may then be assembled in a more traditional package, e.g. a ball-grid array (BGA), or assembled directly on a printed circuit board (PCB), similar to wafer-level chip-scale packages (WL-CSP). By way of illustration, an example thereof is shown in FIG. 1, indicating a packaged chip making use of an interconnect substrate. A chip 10 is shown being assembled to a through silicon via interposer substrate 20 which is 3D wafer level packaged. Between the interposer substrate 20 and the chip 10 multilayer thin film layers 30 or CMOS back end of line (BEOL) layers typically are present. Connection with the next level of assembly is obtained via through-silicon-vias. In the present example, the next level of assembly is a laminate interposer board 40, which itself can be contacted via a ball grid array or chip-scale packaging solder balls 50. To obtain reliable packaging underfill 60 and transfer moulding compound encapsulation 70 may be used.
In this approach the moulding compound on the interposer wafer with mounted die causes wafer-bow as the assembly is strongly asymmetric. One known solution for preventing wafer-bow is selecting a transfer moulding compound encapsulation with a thermal expansion coefficient similar to that of the wafer used, however a perfect match across the temperature ranges of interest (typically: −55° C. to +300° C.) is not achievable as these compounds consist of a mixture of organic (high CTE, Coefficient of Thermal Expansion) and inorganic compounds (low CTE), where both the Young modulus, E, and Coefficient of Thermal Expansion, CTE, vary significantly as a function of temperature and differ from the temperature variations of E and CTE of the semiconductor devices used. Furthermore the encapsulation with moulding compound causes an increase in thermal resistance of the devices.
US2006/267213 by Ozguz et al., describes a stackable tier structure with one or more integrated circuit dies and one or more feedthrough structures. The dies thereby are positioned into the window of a window substrate. The input/output pads of the integrated circuit die are electrically rerouted using conductive traces from the first side of the tier structure to a feedthrough in the window substrates, to a second side of the tier structure. Stacked tiers can also obtained by stacking different window substrates, each having its die and by electrically connecting these using the feedthroughs in the window substrates.